EXTSEL=LPTNT0, DBGMD=RUN, CMPTMD=DISABLED, CMPIEN=DISABLED, RUN=STOP, CMD=FREE, OVFIEN=DISABLED, CMPRSTEN=DISABLED, OVFTMD=DISABLED
Module Control
| CMD | Count Mode. 0 (FREE): The timer is free running mode on the RTCn module clock (RTCnOSC or LFOSCn). 1 (RISING_EDGE): The timer is incremented on the rising edges of the selected external trigger (LPTnTx). 2 (FALLING_EDGE): The timer is incremented on the falling edges of the selected external trigger (LPTnTx). 3 (ANY_EDGE): The timer is incremented on both edges of the selected external trigger (LPTnTx). |
| EXTSEL | External Trigger Source Select. 0 (LPTNT0): Select external trigger LPTnT0 (PB3.2). 1 (LPTNT1): Select external trigger LPTnT1 (PB3.8). 2 (LPTNT2): Select external trigger LPTnT2 (PB3.9). 3 (LPTNT3): Select external trigger LPTnT3 (Comparator 0 Output). 4 (LPTNT4): Select external trigger LPTnT4 (RESERVED). 5 (LPTNT5): Select external trigger LPTnT5 (RESERVED). 6 (LPTNT6): Select external trigger LPTnT6 (RESERVED). 7 (LPTNT7): Select external trigger LPTnT7 (RESERVED). 8 (LPTNT8): Select external trigger LPTnT8 (RESERVED). 9 (LPTNT9): Select external trigger LPTnT9 (RESERVED). 10 (LPTNT10): Select external trigger LPTnT10 (RESERVED). 11 (LPTNT11): Select external trigger LPTnT11 (RESERVED). 12 (LPTNT12): Select external trigger LPTnT12 (RESERVED). 13 (LPTNT13): Select external trigger LPTnT13 (RESERVED). 14 (LPTNT14): Select external trigger LPTnT14 (RESERVED). 15 (LPTNT15): Select external trigger LPTnT15 (RESERVED). |
| TMRSET | Timer Set. 1 (SET): Writing a 1 to TMRSET initiates a copy of the value from the DATA register into the internal timer register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software. |
| TMRCAP | Timer Capture. 1 (SET): Writing a 1 to TMRCAP initiates a read of internal timer register into the DATA register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software. |
| CMPSET | Timer Comparator Set. 1 (SET): Writing a 1 to CMPSET initiates a copy of the value in DATA into the internal timer comparator register. This field is automatically cleared by hardware when the copy is complete and does not need to be cleared by software. |
| CMPCAP | Timer Comparator Capture. 1 (SET): Writing a 1 to CMPCAP initiates a read of the internal comparator register into the DATA register. This field is automatically cleared by hardware when the operation completes and does not need to be cleared by software. |
| OVFIEN | Timer Overflow Interrupt Enable. 0 (DISABLED): Disable the timer overflow interrupt. 1 (ENABLED): Enable the timer overflow interrupt. |
| CMPIEN | Timer Compare Event Interrupt Enable. 0 (DISABLED): Disable the timer compare event interrupt. 1 (ENABLED): Enable the timer compare event interrupt. |
| OVFTMD | Timer Overflow Toggle Mode. 0 (DISABLED): Timer overflows do not toggle the Low Power Timer output. 1 (ENABLED): Timer overflows toggle the Low Power Timer output. |
| CMPTMD | Timer Compare Event Toggle Mode . 0 (DISABLED): Timer compare events do not toggle the Low Power Timer output. 1 (ENABLED): Timer compare events toggle the Low Power Timer output. |
| CMPRSTEN | Timer Compare Event Reset Enable. 0 (DISABLED): Timer compare events do not reset the timer. 1 (ENABLED): Timer compare events reset the timer. |
| DBGMD | Low Power Timer Debug Mode. 0 (RUN): The Low Power Timer module will continue to operate while the core is halted in debug mode. 1 (HALT): A debug breakpoint will cause the Low Power Timer module to halt. |
| RUN | Timer Run Control and Compare Threshold Enable. 0 (STOP): Stop the timer and disable the compare threshold. 1 (START): Start the timer running and enable the compare threshold. |